JEDEC JEP69-B (R1999)
PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS
standard by JEDEC Solid State Technology Association, 11/01/1973
- Comments Off on JEDEC JEP69-B (R1999)
- JEDEC
PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS
standard by JEDEC Solid State Technology Association, 11/01/1973
SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT
standard by JEDEC Solid State Technology Association, 01/01/2018
Multi-wire Multi-level I/O Standard
standard by JEDEC Solid State Technology Association, 06/01/2016
ADDENDUM No. 11A.01 to JESD8 – 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 – 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007
STEADY-STATE TEMPERATURE HUMIDITY BIAS LIFE TEST
standard by JEDEC Solid State Technology Association, 07/01/2015
COMPONENT QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS (INCLUDING ADMINISTRATIVE QUALITY PROBLEMS)
standard by JEDEC Solid State Technology Association, 12/01/1999
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS
standard by JEDEC Solid State Technology Association, 12/01/2010
GUIDELINES FOR PACKING AND LABELING OF INTEGRATED CIRCUITS IN UNIT CONTAINER PACKING
standard by JEDEC Solid State Technology Association, 02/01/2006
Universal Flash Storage (UFS)
standard by JEDEC Solid State Technology Association, 09/01/2013
Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices
standard by JEDEC Solid State Technology Association, 08/01/2012